1. Field of the Invention
This invention relates generally to the field of analog-to-digital converters and more particularly, this invention relates to analog-to-digital converters which employ multiple neural network converters for simultaneously processing more than one sample.
2. Description of the Prior Art
A wide variety of electronic circuit designs for analog-to-digital converters (referred to hereinafter as A/D converters) are known in the art. Designs vary from "flash" A/D converters which are capable of converting an analog voltage into a digital signal in essentially a single clock pulse, to various other designs which, though they are not as fast as flash converter designs, accomplish conversion with fewer components.
It is understood that in general, there is a trade-off between circuit size and speed in A/D converters. Conventional successive approximation A/D converters are relatively small in size, however, they require a relatively large number of clock cycles to provide an accurate digital representation of the input analog voltage. In contrast, flash A/D converters, as noted, produce an output in essentially only a single clock cycle, however, the circuitry for this design is much more complex. This design requires a resistor ladder network having 2.sup.n +1 resistors for 2.sup.n stages, each of which includes a comparator in addition to decoding circuitry. Thus, the circuit requires a relatively large array of solid state devices for implementation and is impractical for certain applications.
While various designs in the prior art have attempted to achieve an ideal balance between circuit size and conversion speed, there remains a need in the art for A/D converter designs which provide high speed, accurate conversions with a minimum amount of circuitry.
Some more recent approaches have included adaptive referencing circuitry such as that disclosed in U.S. Pat. No. 4,987,417 invented by Buckland. In this design, the outputs from higher-order comparators feed forward through a resistor network to the voltage reference inputs of lower-order comparators. This forms a neural network for performing the conversion wherein the comparison voltage for a given comparator depends on the output of higher-order comparators. The conversion performed by this design, however, is not complete until each comparator produces a stable output. More recently, novel approaches to the design of the A/D converter neural network and latching of the outputs from the neural network have produced further advances. These A/D converter designs are disclosed in my co-pending U.S. patent application, Ser. No. 08/254,986, filed Jun. 7, 1994, titled Latched Neural Network A/D Converter, which is incorporated herein by reference.
The Latched Neural Network A/D Converter application discloses an A/D converter with a neural network which employs a register to store the outputs from a plurality of comparators after each step in the conversion process. The outputs from the register corresponding to higher-order bits are fed forward to a plurality of voltage sources such as either an R/2R resistor ladder network or the inputs of a plurality of D/A converters to alter the reference voltages for the lower-order voltage comparators. This design produces a circuit with adaptive referencing capabilities which enables the use of fewer components to accomplish the conversion process. It is an improvement over the prior art neural network A/D converters because it provides greater flexibility in that it is easier to implement a converter with a greater number of stages. The prior art neural network A/D converters are of limited utility because increased circuit complexity is required for higher resolution and is therefore impractical for many high resolution applications.
The above-referenced application also discloses the ability to operate the improved circuitry with fewer neural network conversion steps while maintaining a high degree of accuracy. When operating the neural network A/D converter with a limited number of steps, the conversion may be considered complete after a fixed number of steps or after additional circuitry senses the conversion is complete for a given sample.
A further advance is disclosed in my co-pending application, Ser. No. 08/254,988, filed Jun. 7, 1994, titled, Combined Conventional/Neural Network Analog-to-Digital Converter, which is also incorporated herein by reference. This application describes an A/D converter which combines both conventional A/D converter circuitry and the improved neural network disclosed in application Ser. No. 08/254,986 to further improve conversion speed without sacrificing a corresponding amount of accuracy. In this application, a high speed conventional converter converts the higher-order bits and a neural network converts the lower-order bits. The increased conversion speed for the overall converter justifies the additional circuitry necessary for implementation of the high speed conventional converter. In a preferred embodiment, a flash A/D converter converts the higher-order bits of the analog signal. It is understood that any conventional A/D converter will provide satisfactory results, however, a flash converter allows realization of higher overall converter speeds. The results from the flash converter feed forward into the higher-order bits of a plurality of D/A converters which provide the reference voltages for a plurality of voltage comparators that determine the outputs for the lower order-bits. The outputs from the voltage comparators are applied to inputs of a register which temporarily stores the results. The outputs from the more higher-order outputs of the register feed forward into the D/A converters which provide the reference voltages for the lower-order comparators. This design forms a neural network for converting the lower-order bits wherein outputs from the conventional or high speed portion of the converter and the higher-order outputs from the neural converter feed-forward and determine the reference voltages for lower-order comparators in the neural network. In an alternate design, voltage sources other than D/A converters such as biased resistor ladder networks may be used to act as voltage sources for the comparators. This circuit can also use the technology disclosed in application Ser. No. 08/254,988 for limiting the number of neural network conversion steps necessary for completing conversion while maintaining conversion accuracy.
While these designs have improved the speed of A/D converters and/or decreased the circuity necessary for implementation, there remains a need in the art for fast A/D converters with high resolution and limited circuit complexity. It is therefore an object of the present invention to provide a high resolution, high speed A/D converter which performs the conversion process with a limited number of steps.